Bipolar MOS logic circuit and semiconductor integrated circuit
US5057713A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 1990 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Feb 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An invention is disclosed, which is suitable for operating a bipolar-MOS logic circuit, and in particular Bi-CMOS logic circuit with a low power supply voltage below 5V, e.g. around 3V. According to the present logic circuit, since the base current of a second NPN transistor is supplied from a power supply through a PMOS transistor (first current switching means), the impedance of which is lowered previously by a logic inverting means and an NMOS logic circuit (second current switching means), which is on/off controlled by an input signal, in a transient logic level transition period where the output is switched from the level "1" to "0" (i.e. it falls), it is possible to supply a sufficient base current to the second NPN. In this way, it is possible to turn-on the second NPN with a high speed and to pull down to the level "0" with high speed. Further, since the PMOS is switched off owing to the action of the logic inverting means just after having allowed a sufficient base current flow therethrough, the current path, through which the base current of the second NPN is supplied, is stopped and thus DC power consumption is elimated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.