Phase-locked timebase for electro-optic sampling
US5057771A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1990 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Jun 18, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/308
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A phase-locked timebase for electrical and electro-optic sampling has an offset phase-locked loop for controlling the delay between a stimulus reference signal and a sample strobe signal. A reference signal source synchronizes a stimulus source for a device under test and also is input to the phase detector of a phase-locked loop. Also input to the phase-locked loop in the baseband section is a sample phase control signal. The output of the offset phase-locked loop is an integer multiple of the reference signal source that is delayed from the reference signal source by a controlled amount. The output of the offset phase-locked loop is input to a low noise synchronous detection circuit that mixes a response signal from the device with an impulse sample strobe generated from the output of the phase-locked loop. The mixed response signal is detected, integrated and output at a rate equal to or much lower than the sample rate, as determined by the integration time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.