Double-gated semiconductor memory device
US5057898A · kind A · utility
42Cited by
4References
9Claims
0Family size
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Key dates
| Filing date | Nov 20, 1990 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Nov 20, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A double-gated MOS type semiconductor memory device having a pair of inverters each of which comprises a bulk MOS transistor formed in a semiconductor substrate and having a first gate electrode on the substrate, and a complementary type MOS transistor stacked over and connected with the bulk MOS transistor, the complementary tyupe MOS transistor being composed of a first insulating film, a semiconductor active layer, a second insulating film and a second gate electrode, laminated upwardly in this order on the first gate electrode, and a process for preparing the double-gated MOS type semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.