Microprocessor having a protection circuit to insure proper instruction fetching
US5057999A · kind A · utility
15Cited by
12References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1989 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Jun 26, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0763
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor including a CPU, an instruction memory (ROM) with a sequencer in the CPU that sends out a fetch signal for an instruction, and an address decoder that decodes the fetch signal and sends a signal to the ROM allowing the fetch signal to fetch an instruction if the address is correct.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.