Memory device having address control function
US5058064A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1989 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Dec 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory device having unmultiplexed address inputs for performing an address control function including an address control input (AC) port, address inputs and an address arithmetic unit which performs the address control function by summing up these inputs. These units are connected such that the summed address of the address inputs and the address control input is applied to the memory as the actual address. Also provided is a memory device having multiplexed address inputs for performing an address control function including an address control input (AC) port, a row address select input (RAS) port, and an address arithmetic unit for performing an address control function by controlling these ports. The ports are connected such that, when considering the address actually applied from the multiplexed address input, the address control input (AC), and the row address select input (RAS), if the RAS signal was applied, the sum of the row address select input and the address control input (AC) is applied to the memory as the actual lower address, and if the column address select input (CAS) was applied, the sum of the address input and the carry produced by lower address is applied to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.