Individual bit line recovery circuits
US5058067A · kind A · utility
11Cited by
1References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 6, 1990 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Jun 6, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bipolar recovery circuit for a static random access memory cell is described. The circuit corrects reverse emitter-base breakdown which occurs in the known common base node writing recovery circuits. The circuit is simple, requiring little silicon chip area to fabricate. In a preferred embodiment, a separate recovery circuit is coupled to each of the true output line and the complement output line of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.