Programmable fault insertion circuit
US5058112A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1989 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Jul 31, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault insertion circuit is disclosed which generates and applies a fault signal to a digital circuit under test. The fault insertion circuit includes fault insertion hardware connected to the digital circuit under test. The fault insertion hardware is arranged to select, generate and apply the fault signal. A programmable controller and communication circuit are also included. The communication circuit is connected to the controller and to a data terminal, personal computer or any other source of programming commands and instructions. The communication circuit receives the programming commands and instructions from the data terminal and transmits the commands and instructions to the controller. The controller in response to the received commands and instructions transmits control signals to the fault insertion hardware, thereby, generating and applying a fault signal to the digital circuit under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.