Clock distribution system and technique
US5058132A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1989 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Oct 26, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock distribution device (CDD) (100) is used in a concentrator (200,300) to distribute multiple bits of serial data (208) in parallel across back plane boards (Board A, B, N. NN) as a byte-wide data signal (214). Each back plane board (Board A, B, N, NN) has a CDD (100). One back plane board (Board A) has a master oscillator (120) which generates a local low frequency reference clock signal (212). The reference clock signal (212) is distributed to all of the back plane boards (Board A, B, N, NN) where each board's CDD (100) uses the reference clock signal (212) to generate a high frequency clock signal (TXCLK) and a plurality of local phase separated clock signals (LBC1-LBC5). Each board has a receiver (156a) and a transmitter (156b) and the low frequency clock signals (LBC1-LBC5) are employed to synchronize and deskew the parallel data signal (214) transmitted across the back plane from board to board by using the local phase separated clock signals (LBC1-LBC5) generated on each board to strobe out the serial data (208) from the receiver (156a) in parallel as the parallel data signal (214), to latch in the parallel data signal (214) into a latch (LATCH) internal to the transmit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.