Single circuit for detecting a frame synchronization pattern and generating control signals
US5058141A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1990 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Mar 1, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A single circuit for detecting a synchronization pattern in a serial data stream. Subsequent to detecting the synchronization pattern, the single circuit generates the control signals for converting the serial data to a parallel format and loading the parallel data into a first-in-first-out (FIFO) memory. The single circuit includes a controller arranged to receive the serial data stream. A counter is connected to the controller. When the counter is detecting the synchronization pattern and the synchronization pattern is being received, the counter is incremented. Absent the synchronization pattern being received, the counter is reset to a predetermined starting point. Subsequent to detecting the synchronization pattern, the counter generates a load signal. The single circuit further includes a pulse generator arranged to receive the load signal from the counter and generate a pulse of duration equal to a bit period of the serial data stream. An indicator is provided which generates an in-synch signal after the counter detects the synchronization pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.