Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5059924A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1990 |
| Grant date | Oct 22, 1991 |
| Priority date | — |
| Expiry date | Apr 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0638
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates a plurality of signals (10a-10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher or lower than the frequency 10a-10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal (9) is delayed or advanced by an appropriate amount. In the preferred embodiment, the phase locked loop is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.