Method and apparatus for transparently switching clock sources
US5059925A · kind A · utility
99Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1990 |
| Grant date | Oct 22, 1991 |
| Priority date | — |
| Expiry date | Sep 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for stably maintaining an output clock signal from a phase-locked loop (PLL) frequency multiplier when switching from one clock source to another clock source is described. This method and apparatus maintains the phase relationship between the external signal to the phase detector and the feedback signal from the divider to the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.