Output buffer with enhanced electrostatic discharge protection
US5060037A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 1990 |
| Grant date | Oct 22, 1991 |
| Priority date | — |
| Expiry date | Jul 10, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
Abstract
A CMOS output buffer is disclosed, which provides ESD protection by incorporating a low resistance path within the p-channel pull-up device. Output buffers according to the prior art can be damaged by ESD occurring at the output terminal having a positive polarity, as the drain-to-substrate diode of the pull-down transistor breaks down in the reverse-bias direction, especially when second breakdown occurs. The p-channel pull-up device, formed within an n-well, is fabricated to have n-type diffusions disposed near to the p-type drain diffusions. The distance between the n-type diffusion and the drain diffusions in the pull-up device reduces the series "on" resistance of the drain-to-n-well diode of the pull-up device, to a level which keeps the voltage at the output terminal below the reverse-bias breakdown voltage of the drain-to-substrate diode in the pull-down device. The pull-up device may be constructed in a ladder structure to facillitate the reduction of this resistance. A further embodiment of the invention is disclosed which provides the same protection to the n-channel pull-down device, by way of an n-well diode with low series resistance, for open-drain or other pull-up c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.