Multiple resistivity wiring apparatus
US5060049A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 18, 1990 |
| Grant date | Oct 22, 1991 |
| Priority date | — |
| Expiry date | Jul 18, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ceramic multilayer wiring substrate is provided on which the metallized wirings are partially altered to provide multiple resistivities without changing the other electrical properties associated with a particular physical wiring geometry. Sequentially positioning conductive materials of different resistivities along the length of each individual wiring produces a final wiring pattern where each individual wiring can have a different resistance from the other wirings. A multiple resistivity wiring pattern can maximize the operation of a semiconductor chip attached thereto, for example, by reducing the effect of electronic noise on the semiconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.