Read only memory with write operation using mask
US5060190A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1990 |
| Grant date | Oct 22, 1991 |
| Priority date | — |
| Expiry date | Sep 18, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FET ROM and a manufacturing process in which ROM's can be stockpiled after the gates have been formed and the source and drain implants have been made but before the write operation has been performed. At this stage, the unwritten ROM has an array of enhancement mode FET's connected in a logical NAND configuration with an overlying layer of insulation. For a write operation, the insulation is removed to expose the drain and source regions of the FET's, a conductive layer is formed over the array, and the layer is selectively etched to leave a short circuit element between the drain and source of those FET's that are to store a binary 0 and to leave switchable the FET's that are to store a 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.