Monophase logic
US5061864A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1990 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Jun 18, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Intermediate path splitting circuit arrangements are coupled between the input node and output stage of an IC defining a plurality of different signal propagation paths. A relatively higher speed output pullup turn on signal progagation path is coupled between the input node and the output pullup transistor element for turning on the output pullup transistor element at relatively higher speed in response to a first input data signal. A relatively slower speed output pulldown turn off signal propagation path turns off the output pulldown transistor element at a relatively slower speed in response to the first data input signal. Similar circuit arrangements are provided for relatively high speed turn on of the pulldown transistor element and relatively low speed turn off of the pullup transistor element. Control of turn on and turn off of the respective output pullup and pulldown transistor elements is from separate output driver nodes for higher speed operation. The separate split paths are provided by sequences of internal stages with skewed conductance pullup and pulldown elements. A cutoff circuit cuts off the output pullup and pulldown transistor elements a time delay after tran…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.