Phase equalization system for a digital-to-analog converter utilizing separate digital and analog sections
US5061925A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1990 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Aug 22, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response. The nonlinear phase response of the interpolation filter (52) compensates for the phase deviation of the analog filter (22) from a linear phase response. Therefore, the composite phase pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.