VLSI triple-diffused polysilicon bipolar transistor structure
US5061982A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1990 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Jan 8, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/641
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop (32) and locally oxidizing a P-doped silicon substrate (21) to define a collector region, implanting an N-type collector (43) and diffusing the implants (40, 44). Device emitter, collector and base contact features (64, 66, 68) are photolithographically defined by two openings (54, 56) spaced lengthwise along the collector region. Low resistivity P- and N-type regions (74, 80) are implanted in the substrate in the openings and covered by local oxidation (86, 88). The collector region is preferably formed in a keyhole shape with a wide collector contact feature (66B) and adjoining region 80B and narrow base contact (68B) and emitter (64B) features and intervening region (74B). The substrate (22) is exposed in the emitter and contact features. A single polysilicon layer (94) is deposited, selectively doped and oxidized to form separate base, collector and emitter contacts (94) and a triple diffused NPN transistor (116, 92, 40).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.