Temporary bus master for use in a digital system having asynchronously communicating sub-systems
US5062044A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1987 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Sep 29, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit embodied in a single integrated circuit, which is connected through an asynchronous communication bus to a primary bus master and a permanent bus slave, cooperates with the master and slave in a multi-master transfer of a block of data having a leading sub-block of data followed by a trailing sub-block of data. The slave operates in accord with request/acknowledge protocol by applying at least one request signal to a conductor of the bus and responding to each of a consecutive sequence of acknowledge signals on a second conductor of the bus from the master in communication of each of a consecutive sequence of concurrently-applied parallel-by-bit data carried by multiple other conductors that define a data bus portion of the communication bus. The circuit selectively responds to each of a predetermined number of acknowledge signals from the master during communication of the leading sub-block, by copying each data item of the leading sub-block, so that the leading sub-block is distributed to the circuit as it is communicated between the master and the slave. The circuit selectively responds to request signals by applying a second predetermined number of acknowledge signals…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.