Programmable multiplexing techniques for mapping a capacity domain into a time domain within a frame
US5062105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1990 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Jan 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0046
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Method and apparatus are disclosed for a programmable multiplexer for converting each of one or more input data signals, with individual data rates, into a second higher data rate signal by mapping contiguously arbitarily assigned Capacity Time Slots (CTSs) in a capacity domain frame to Time Slots in a Time Domain frame (TDTSs) so the TDTSs for each input signal are substantially uniformly spread throughout the TD frame. The programmable multiplexer receives separate input data rate signals which are clock synchronized to the multiplexer clock from separate synchronizers, and maps the capacity domain of the input signals to the time frame format using a 2-step or 3-step digit reverse technique. Both techniques decompose the capacity domain address into predetermined digits from predetermined number bases and then combine the digits to perform a similar computation using the number bases in reverse order. The 3-step technique uses an intermediate step of translating the initially determined values for each the predetermined digits using a bit reversal technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.