Delay-locked loop circuit in spread spectrum receiver
US5062122A · kind A · utility
86Cited by
1References
12Claims
0Family size
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Inventors
Key dates
| Filing date | Sep 28, 1988 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Sep 28, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/70712
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Spread spectrum receiver includes a delay locked loop (DLL) circuit for holding the synchronization of a despread signal with a received spread spectrum signal. The DLL circuit comprises a subtracter for generating a signal representative of a subtraction between first and second correlation signals, a positive feedback amplifier for amplifying the subtraction representative signal and a window comparator for producing a lock signal when the subtraction representative signal is positioned within a window width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.