Channelized delay and mix chip rate detector
US5063572A · kind A · utility
5Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1990 |
| Grant date | Nov 5, 1991 |
| Priority date | — |
| Expiry date | Jun 4, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04K3/228
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A detector circuit for indicating the chip rate of a direct sequence frequency hopped data transmission signal. The wide band input signal is channelized into L adjacent sub-bands and each sub-band signal is multiplied by a delayed copy of itself and then hard limited, after which all the hard limited product signals are totalized to give a resultant signal representative of the chip rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.