Biasing circuits for field effect transistors using GaAs FETS
US5065043A · kind A · utility
5Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1990 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Mar 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/226
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Hysteresis effects in low frequency field effect transistor circuits are minimized by using biasing or clamping circuits including field effect transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.