Semiconductor logic circuit with noise suppression circuit
US5065048A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1989 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Aug 23, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00338
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.