Phase-locked loop bandwidth switching demodulator for suppressed carrier signals
US5065107A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1990 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Apr 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0081
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver for tracking a carrier suppressed phase-shifted input signal comprises a phase-locked loop circuit for receiving the input signal and having a variable frequency oscillator responsive to a control signal for oscillating at a frequency corresponding to an intermediate frequency and a frequency difference detector for producing an output signal indicative of the frequency difference between the frequency of the input signal and the intermediate frequency, a feedback loop network having a narrow-band path and a wide-band path and being responsive to the detector output signal for producing the control signal and applying the control signal to the oscillator through one of the paths whereby to change the intermediate frequency of the oscillator in response to the control signal, a quality detector responsive to the detector output signal for producing a signal corresponding to the bit error rate of the input signal; and selection means responsive to the bit error rate signal for causing the control signal to pass through the narrow-band path when the bit error rate signal is below a predetermined threshold and through the wide-band path when the bit error rate signal exceeds…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.