Graphic display system for process control using a plurality of displays connected to a common processor and using an FIFO buffer
US5065343A · kind A · utility
35Cited by
7References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1989 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Feb 14, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2352/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphic display system comprising a plurality of graphic display units which are connected to a host processor through a common bus and providing useful quick response characteristics as a man-machine interface for process control, wherein a common memory of two ports, one of which is connected to the common bus and the other is connected to an internal bus, is provided in each graphic display unit and a part of the common memory is used for transmission of high level command/data with the host processor and comprises a FIFO (i.e. first in first out) buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.