Shared use of keyboard and memory lines
US5065356A · kind A · utility
18Cited by
4References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1988 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Dec 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention describes a method and apparatus for interconnecting keyboard lines and memory lines to the same pins of a microprocessor or calculator chip. Resistors are placed in series with each keyboard line before interconnection to the memory lines and microprocessor pins to prevent disruption or degradation of the memory signal in the event a key on keyboard is depressed during a memory operation cycle. Means are provided to prevent memory operations during keyboard scan routines and means are provided to prevent keyboard scan routines from operating during memory operation cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.