Non-volatile RAM with integrated compact static RAM load configuration
US5065362A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1989 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Jun 2, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/0063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile random access memory (NVRAM) cell of condensed size employs a pair of programmable threshold voltage devices, e.g. MNOS (metal nitride oxide semiconductor), SNOS (silicon nitride oxide semiconductor), SONOS (silicon oxide-nitride-oxide semiconductor) or floating gate transistors, in which different threshold voltage levels are established in accordance with the data signal levels existing on the data nodes of a flip flop, when the volatile data is stored in the programmable devices. During recall of the non-volatile stored data to the data nodes of the flip flop, the programmable devices actively conduct current to the data nodes to set the flip flop in the same state that existed when the data was stored. Power is supplied to the flip flop independently of the power supplied to the programmable devices. A single polysilicon conductor forms gates of transistors which connect the programmable devices to the data nodes and the gates of the flip flop transistors. A load device for each data node is integrated in the single polysilicon conductor. A dynamic program inhibit capability is achieved in each programmable device during the store operation, by applying a series …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.