Non-volatile RAM bit cell
US5065366A · kind A · utility
1Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1990 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Jul 17, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell comprising a bistable latch having first and second nodes, at least two non-volatile transistors (NV1, NV2) each having a source, a drain and a control gate, the control gates being connected to the first node (NODE 1) and one of the source and drain of each transistor being connected to the second node (NODE 2), each non-volatile transistor (NV1, NV2) further having a substrate and a floating gate between the control and the substrate, and switching means (N1, N2, TG1) for enabling the transistors to be checked in circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.