Process and circuit arrangement for digital control of the phase of scanning clock pulses
US5065412A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1989 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Aug 29, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
For conversion of digital signals received in analog form, scanning samples of these digital signals are sent to a digital signal receiving unit at intervals fixed by the occurrence of the scanning clock pulses after an analog-digital conversion. The respective digital signal receiving unit then supplies the phase control signals derived from the received digital signals. After filtering, these phase control signals are sent at given intervals to a clock generator for delivering the scanning clock pulses. The phase control signals are filtered in the form EQU Ta(i)=a1(Te(i)-a2 Te(i-1))+a3 Ta(i-1) where a1, a2 and a3 are filter coefficients, Ta(i) and Ta(i-1) are filtered phase control signals at the times i and (i-1) and Te(i) and Te(i-1) are phase control signals made available at the times i and (i-1). The filtered phase control signals are then sent to the clock generator in quantized form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.