Method of forming wiring of a semiconductor device
US5066612A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1991 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Jan 3, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the course of a production of a semiconductor device with a multilayer insulating layer, when a contact hole is opened in the multilayer insulating layer, an insulating layer activating a metal selective vapor-growth appears at the side wall of the contact hole. A thin metal (e.g., tungsten) layer is selectively deposited in the contact hole. In another case, another metal layer appears within the contact hole. An insulating film preventing a metal selective vapor-growth is deposited over the whole surface of the side wall of the contact hole, the metal layer and a top surface of the multilayer insulating layer, and is anisotropically etched to leave a portion of the film lying on the side wall only as a side wall insulating film. The contact hole is completely filled with another metal (tungsten) by a selective vapor-growth method, to flatten an exposed surface, and then a conductor (e.g., aluminum) line layer is formed on the metal layer in the contact hole and the multilayer insulating layer, to thereby complete the wiring structure of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.