Apparatus for generating phase shifted clock signals
US5066868A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1990 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Aug 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock phase shifting circuitry includes a cascade connection of inverting amplifiers for generating a plurality of relatively delayed clock signals. Buffer amplifiers couple alternate ones of the inverting amplifiers to a clock phase selection circuit for providing a desired one of said plurality of delayed clock signals. A capacitor is coupled between the output of each inverting amplifier and a point of constant potential. Respective circuits, having an input impedance which emulates the input impedance of the buffer amplifiers, are coupled to the output connections of the inverting amplifiers located between said alternate inverting amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.