Circuit for converting ECL level signals to MOS level signals
US5066876A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1990 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Dec 21, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor circuit has a first and a second transistor differentially connected with each other and having bases receiving an input signal therebetween; a first and a second resistor respectively connected between collectors of the first and second transistors and a first power supply terminal; a third transistor having an emitter receiving a voltage dropped by the first resistor and a collector connected to an output terminal; a fourth transistor having an emitter receiving a voltage dropped by the second resistor; and a fifth transistor having a collector connected to the output terminal and an emitter connected to the second power supply terminal. Biasing voltages are provided to bases of the third and fourth transistors thereby causing the fourth transistor to be conductive when the voltage dropped by the first resistor is larger than the voltage dropped by the second resistor and causing the third transistor to be conductive when the voltage dropped by the first resistor is smaller than the voltage dropped by the second resistor. The fifth transistor become conductive when the fourth transistor is in a conductive state. The circuit is capable of operating in a high speed and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.