Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
US5067071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1985 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Feb 27, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor sys…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.