Cache which provides status information
US5067078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1989 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Apr 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also coupled to the main memory primarily via a secondary bus but also via the M bus. External TAGs coupled between the M bus and the secondary bus are used to maintain coherency between the first and second processing systems. Each external TAG corresponds to a particular cache/MMU integrated circuit and maintains information as to the status of its corresponding cache/MMU integrated circuit. The cache/MMU integrated circuit provides the necessary status information to its corresponding external TAG in a very efficient manner. Each cache/MMU integrated circuit can also be converted to a SRAM mode in which the cache performs like a conventional high speed static random access memory (SRAM). This ability to convert to a SRAM provides the first processing system with a very efficient scratch pad capability. Each cache/MMU integrated circuit also provides hit information external to the cache/M…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.