Method and apparatus for mapping a digital signal carrier to another
US5067126A · kind A · utility
74Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1989 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Aug 4, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/907
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A DS-3 to 28 VT1.5 SONET Interface Circuit is shown, without using standard intermediate DS-2 and DS-1 Desynchronizer Phase-Lock Loops. The elimination of DS-2 and DS-1 Desynchronizer Phase Lock Loops results in a significant reduction in cost and complexity of SONET interface circuits for the existing asynchronous digital multiplex hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.