Digitally controlled timing recovery loop
US5068628A · kind A · utility
55Cited by
6References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1990 |
| Grant date | Nov 26, 1991 |
| Priority date | — |
| Expiry date | Nov 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.