Programmable interconnect or cell using silicided MOS transistors
US5068696A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1990 |
| Grant date | Nov 26, 1991 |
| Priority date | — |
| Expiry date | Aug 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/235
Abstract
A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.