Optical full adder
US5068815A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1990 |
| Grant date | Nov 26, 1991 |
| Priority date | — |
| Expiry date | Jun 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06E1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SUM and CARRY output signals of a first optical half adder are provided to one input terminal of a second optical half adder and an optical latch memory, respectively, and an output signal of the optical latch memory is provided to the other input terminal of the second optical half adder. Input and output of the two optical half adders and optical latch memory are performed through an optical signal. Each optical half adder includes two light-receiving elements each having a symmetrical electrode arrangement in which two Schottky junctions are connected to each other opposite in polarity, and peripheral elements of resistors, a capacitor and an amplifier. The optical latch memory is an optical flip-flop memory in which a high-speed light-receiving element produces an electric signal in response to an input optical signals, and a high-speed light-emitting element produces, in response to the electric signal guided from the light-receiving element, feed-back light to be applied to the light-receiving element and an output optical signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.