Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof
US5068823A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1988 |
| Grant date | Nov 26, 1991 |
| Priority date | — |
| Expiry date | Jul 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus architecture is provided which permits an easily programmed apparatus to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus is connected to a communications bus which receives apparatus parameter and topological information from a host processor and/or memory. The apparatus includes numerous functional blocks, a core, and a parametric bus. The functional blocks such as serial and parallel ports, D/A and A/D converters, biquad filters, etc. serve to process signal data and are connected in any desired manner through a switching matrix located in the core. The topology of the switching matrix is received via the communication bus. Parameters for the functional blocks are sent to the functional blocks via the communications bus, the core, and the parametric bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports and via the D/A and A/D converters (f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.