Multi-level selecting circuit
US5070255A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1990 |
| Grant date | Dec 3, 1991 |
| Priority date | — |
| Expiry date | Dec 27, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-level selecting circuit has a selecting section provided in a semiconductor chip by a CMOS process for selecting one of a plurality of input levels at a time, input terminals provided on the semiconductor chip for feeding a plurality of levels to the selecting section, and an output terminal provided on the semiconductor chip for outputting one of the plurality of levels having been selected by the selecting section. The selecting section has a plurality of MOS transistors each being provided in the semiconductor chip and connected between respective one of the plurality of input terminals and the output terminal for feeding, when turned on by external control, the input level on the input terminal to the output terminal. Source connecting lines each is connected between respective one of the input terminals and the source electrode of respective one of the MOS transistors for feeding a voltage on the input terminal to the source electrode. A back-gate connecting line is connected between the input terminals and the back-gates of the MOS transistors for feeding a predetermined voltage applied to the input terminals to the back gates. The back-gate connecting line is substan…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.