Full wafer integrated circuit testing device
US5070297A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1990 |
| Grant date | Dec 3, 1991 |
| Priority date | — |
| Expiry date | Jun 4, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31935
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A full wafer integrated circuit testing device (10) tests integrated circuits (15) formed as a wafer in conjunction with a test control unit (40). Probe units (14) associate with respective integrated circuits (15). Probe tips (16) on probe units (14) communicate with respective pads (19) with the integrated circuits (15). Interface circuitry (36) selectively communicates test data between the test control unit (40) and the integrated circuit (15). Test pins (16) have positions on probe units (14) associated with respective integrated circuit connection points (19) for testing associated integrated circuit (15) components. Interface circuitry (36) includes comparators (54 and 56) that compare signals between the integrated circuit (15) and the test control unit (40). Memory components (66 and 68) store data associated with signals from test control unit (40) and said integrated circuit (15). Compliant material (32) assures that probe tips (16) throughout probe card (10) positively and conductively engage integrated circuit pads (19) of all associated integrated circuits (15) of a wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.