Semiconductor structure for high power integrated circuits
US5070382A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1989 |
| Grant date | Dec 3, 1991 |
| Priority date | — |
| Expiry date | Aug 18, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A semiconductor structure for high power integrated circuits is fabricated having a substrate, a first and second epitaxial layer, each having a patterned buried layer, and a third epitaxial layer in which power, logic and analogic devices are formed. The power device is formed in an isolated region of the third epitaxial layer over the buried layers, which provide for good electrical contact to the back of the substrate. The analogic and logic devices are formed in the third epitaxial layer outside the isolated region of the power device. The thickness of the first and second epitaxial layers reduces the NPN parasitic transistor effect. The first epitaxial layer may be fabricated with a lower resistivity to further reduce the parasitic NPN transistor effect. The second epitaxial layer can be of a higher resistivity in order to reduce autodoping of the third epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.