Power on coordination system and method for multiple processors
US5070450A · kind A · utility
45Cited by
16References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1990 |
| Grant date | Dec 3, 1991 |
| Priority date | — |
| Expiry date | May 25, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a first processor, a second processor, a bus shared by the first processor and the second processor, and a power on reset coordination means for the first processor and the second processor. The power on reset coordination means includes means for resetting the first processor and the second processor, and means for deasserting reset to the first processor and second processor sequentially. It should be noted that in embodiments of the present invention, some "other" processor must be "up" in order to reset the "first" processor or to deassert reset to it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.