Forth specific language microprocessor
US5070451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1989 |
| Grant date | Dec 3, 1991 |
| Priority date | — |
| Expiry date | Apr 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A language specific microprocessor for the computer language known as FORTH is disclosed. The microprocessor includes four main registers each for holding a parameter; a L or instruction latch register for decoding instructions and activating microprocessor operation; an I or return index register for tracking returns; an N or next parameter register for operation with an arithmetic logic unit (ALU); and a T or top of parameter stack register with an appended ALU. A return stack port is connected to the I register and a parameter stack port is connected to the N register circuit, each have last in/first out (LIFO) memory stacks for reads and writes to isolated independent memory islands that are external to the microprocessor. The respective I, T and N registers are connected in respective series by paired bus connections for swapping parameters between adjacent registers. A first split 16 bit multiplexer J/K controls the LIFO stack for the I and N registers on paired 8 bit address stacks; a second 16 bit multiplexer designates the pointer to main memory with 65K addresses and an adjoining 65K for data. This addressing multiplexer receives selective input from a program counter P, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.