Defect tolerant set associative cache
US5070502A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1989 |
| Grant date | Dec 3, 1991 |
| Priority date | — |
| Expiry date | Jun 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is desirable to bypass the defects within a cache memory so that a high percentage of the cache is usable; otherwise the entire chip containing the cache memory must be scrapped. Since VLSI chips with a small number of defects form a large proportion of the scrapped yield, rendering chips with a small number of defects usable greatly increases the production yield and reduces the cost of each chip. Therefore, a cache memory is provided wherein each memory location includes a bit which is set in response to a detected hardware defect. Preferably, each memory location in the cache is tested by error detecting software, which sets the defect bit in any memory location containing a defect. The defect bit is tested every time data is retrieved from each memory location, and a set defect bit prohibits further use of a defective memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.