Error limiting analog to digital converter
US5072221A · kind A · utility
46Cited by
7References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1988 |
| Grant date | Dec 10, 1991 |
| Priority date | — |
| Expiry date | Aug 4, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/36
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel analog-to-digital converter having comparators in a sequence with two sets of logic gates having inputs electrically connected to selected primary and complementary outputs of the comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.