Semiconductor integrated circuit having region for forming complementary field effect transistors and region for forming bipolar transistors

US5072285A · kind A · utility

Assignee

• Mitsubishi Electric Corporation · JP

Inventors

• Masahiro Ueda · Toyota, JP
• Toshiaki Hanibuchi · Tokyo, JP
• Kimio Ueda · Itami, JP

Key dates

• Filing date: Feb 22, 1990
• Grant date: Dec 10, 1991
• Expiry date: Feb 22, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/996

Abstract

A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The region for forming p-MOS transistors comprises gates aligned spaced apart from each other in a first direction and p-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming n-MOS transistors comprises gates formed spaced apart from each other in the first direction and n-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming bipolar transistors comprises p-type source or drain region of the region for forming p-MOS transistors as a base region, and an n-type emitter region formed in the base region and a region for taking out the potential of substrate of the p-MOS transistor as a collector region. An npn bipolar transistor formed in the region fo…