Direct memory access controller using prioritized interrupts for varying bus mastership
US5072365A · kind A · utility
21Cited by
9References
8Claims
0Family size
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Key dates
| Filing date | Dec 27, 1989 |
| Grant date | Dec 10, 1991 |
| Priority date | — |
| Expiry date | Dec 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.