Quasi-random digital sequence detector
US5072448A · kind A · utility
3Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1989 |
| Grant date | Dec 10, 1991 |
| Priority date | — |
| Expiry date | Nov 2, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Errors in a predetermined digital sequence are detected by utilizing a detector which includes memory elements such as a series shift register, and logic gates for detecting a predetermined subsequence. Errors are detected by comparing each bit in the data stream with the output of the memory. Logic gates inhibit the detection of an error in response to the subsequence detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.