Main storage access priority control system that checks bus conflict condition and logical storage busy condition at different clock cycles
US5073871A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1988 |
| Grant date | Dec 17, 1991 |
| Priority date | — |
| Expiry date | Sep 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.